Role of Material Gate Engineering in Improving Gate All Around Junctionless (GAAJL) MOSFET Reliability Against Hot-Carrier Effects

Abstract

In this paper, dual-material gate engineering aspect is proposed as an efficient way to enhance the Gate All Around Junctionless (GAAJL) MOSFET devices immunity against hot-carrier effects (HCEs). Analytical models concerning the device analog/RF performance metrics including the degradation related to HCE are developed, where a good agreement with TCAD-based numerical data is recorded. The impact of the defects induced by HCEs on the device analog performance is thoroughly analyzed. Interestingly, promising design strategy based on combining Multi-Objective Genetic Algorithms (MOGAs) with gate engineering paradigm was adopted for bridging the gap between analog/RF performance and improved reliability against HCEs. Moreover, this systematic study has enabled exciting possibilities to the designer for acquiring a comprehensive review regarding the GAAJL MOSFET design reliability-analog/RF performance tradeoffs. Therefore, the proposed design methodology offers a sound pathway to designing high-performance and reliable transistors strongly desirable for nanoelectronic applications.