Co-simulation of AC power noise of CMOS microprocessor using capacitor charging modeling

Abstract

Power noise could decisively impact on the system performance of large-scale integration (LSI), with higher integration and lower power supply voltage. Power noise simulation becomes a key step in the design of LSI systems. This paper presents an original capacitor-charging model that expresses AC part of power consumption current and also demonstrates power noise simulation of a 32 bit microprocessor on a 90 nm CMOS test chip. On-chip power supply voltage and on-board power supply current variations are consistently given by both measurements and simulation.