Low-Power 915MHz CMOS LNA Design Optimization Techniques for RFID

Abstract

According to the definition of noise figure, this paper presents a detailed analysis of the noise parameter of a low noise amplified (LNA) in a CMOS cascode topology with the source degeneration inductance and gate shunt capacitance. Based on the derived equations, the important application of this topology is discussed and a low power UHF CMOS LNA is optimized for RFID. The simulated results show a noise figure of 0.7dB, a power gain of 12.5dB, and an IIP3 of -4dBm while dissipating 2.1mA from a 1.8V supply. As a result, very low noise figures become possible already at very low power consumption levels.