Influences of drain side P+ discrete-islands on ESD robustness in the 60-V pLDMOS-SCR ("PNPNP" arranged-type)

Abstract

How to effectively enhance the reliability robustness in high-voltage BCD processes is an important issue. A p-channel lateral-diffused MOSFET with an embedded SCR which is formed by implanting N⁺ doses in the drain side and divided into five regions, this structure called as the "pnpnp" arranged-type of pLDMOS-SCR in this paper (diffusion regions of the drain side is P⁺-N⁺-P⁺-N⁺-P⁺). Then, altering the layout topology of N⁺ implants in a drain-side P⁺ region is evaluated in this paper by a 0.25-μm 60-V BCD process. In this planning idea, the layout manners of P⁺ region are discrete-islands in the drain-end. From the experimental results, due to all of their secondary breakdown current (I_t2) values are so good reached above 6 A, it can be found that the layout manner of discrete-island distributions in the drain-side have some impacts on the anti-ESD and latch-up immunities. However, the major repercussion is the V_h value will be decreased about 66.7% ~ 73.7%.