Tool for Simulation and Optimization BIST Structures

Abstract

Construction of simulation tool for BIST (build in self test) structures verifying and optimization was described in the paper. This tool uses ISCAS'89 benchmarks as testing circuits. Any testing structures for single and multimodular circuits can be described by means of this tool. Form of testing structures notation is similar to attribute format of VHDL language. Because of large generality this tool is used in process of testing structure verification. A short example of testing structure description was presented in the paper.