Hardware In the Loop for VDM-real time modeling of embedded systems

Abstract

This paper introduces a generic solution for gradually moving from a model of an embedded system to include embedded hardware and software components into the simulation of the model. Our technique enables combined execution (co-execution) of system components models expressed in the VDM-RT formalism with actual hardware/software realizations through the application of Hardware In the Loop (HIL) simulation. Introducing such component realizations in the simulation increases the fidelity of the simulation outcome, thus enabling improved prediction of properties for the system realization.