{"title":"Tri-band CMOS Class-E power amplifier design with phase compensations for polar systems","authors":"C. Lai, W. Tsou, M. Chou, K. Wen","doi":"10.1109/CCECE.2010.5575171","DOIUrl":null,"url":null,"abstract":"A 0.18mm CMOS fully integrated cascode Class-E power amplifier operating in 2.5GHz/3.5GHz/5.2GHz frequency bands for polar transmitters has been proposed. The tri-band amplification is achieved by adaptation of the common-gate transistor size and the matching networks. The phase distortion from supply modulation of the Class-E is compensated by controlling the common-gate transistor gate voltage and a compensative capacitor. Simulation results show that the maximum power-added efficiency (PAE) of 30.4%, drain efficiency of 34% and output power of 18.8dBm from 2.8V supply can be achieved. The phase distortion can be compensated from 34.4° to 3.1° under supply voltage of 0.5V to 2.8V. A system co-simulation has been established for relative constellation error (RCE) evaluation and it reveals that the RCE can be improved from −23.3dB to −31.4dB in 3.5GHz frequency band.","PeriodicalId":325063,"journal":{"name":"CCECE 2010","volume":"142 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"CCECE 2010","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CCECE.2010.5575171","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
A 0.18mm CMOS fully integrated cascode Class-E power amplifier operating in 2.5GHz/3.5GHz/5.2GHz frequency bands for polar transmitters has been proposed. The tri-band amplification is achieved by adaptation of the common-gate transistor size and the matching networks. The phase distortion from supply modulation of the Class-E is compensated by controlling the common-gate transistor gate voltage and a compensative capacitor. Simulation results show that the maximum power-added efficiency (PAE) of 30.4%, drain efficiency of 34% and output power of 18.8dBm from 2.8V supply can be achieved. The phase distortion can be compensated from 34.4° to 3.1° under supply voltage of 0.5V to 2.8V. A system co-simulation has been established for relative constellation error (RCE) evaluation and it reveals that the RCE can be improved from −23.3dB to −31.4dB in 3.5GHz frequency band.