A Novel Approach for Design, Implementation and Construction of Low Density Parity Check (LDPC) Memory

Abstract

Memory is an important part of any digital circuit in which data is stored and retrieved. Technology scaling, lower operating voltages and high integration densities leads for failures in the reliability of memories. The main problem is Single Event Upsets (SEUs) that alters the memories from its normal way of functioning. This paper presents design and implementation of Majority Logic (ML) detecting/decoding on different cyclic codes for error detection and correction. ML decoding method is more capable to detect and correct large number of errors but it takes same high access time for both error and error free codes which impacts memory performance. In this paper, the proposed advanced ML method reduces decoding cycles when there is no error in the data read. The error detection and correction method is done by majority logic decoding and is made effective for Low Density Parity Check (LDPC) codes. This method lowers the power consumption and latency for wide range sizes of code words.