Capacitive impacts of dummies on interconnect propagation performances for integrated circuits of the 65 nm node and below

Abstract

The placement and size of square dummies degrade electrical performances mainly in terms of interconnect capacitance and propagation delay time. Electrical parameters for an isolated interconnect are obtained in a whole spectrum (up to 40 GHz) by electromagnetic modeling. Parasitic effects could be traduced by a fictitious increase of the relative permittivity k-value of inter-level dielectric cutting down performances of porous ULK integration for future 65 and 45 nm technology nodes. The capacitive effect of dummies on the interconnect test structure with a dielectric at k=2.7 was found, in some situations, to be equivalent to that obtained with a dielectric at k=3.2 without dummies. The capacitive effect of dummy distribution was also shown to be generally inhomogeneous, dramatically depending on dummy size and local interconnect design. However, an optimal size of dummies could be determined, leading to an homogeneous capacitive degradation effect, independent of the local interconnect dummy surrounding situation.