An Efficient 5-Transistor SRAM Cell Design using FNSBS-CNTFET for Improving Read and Write Stability

Abstract

In this manuscript, 5-Transistor SRAM Read/Write Assist Techniques based on Fully Nonvolatile Spin-Based Synapse Carbon Nanotube Field-Effect Transistor (FNSBS-CNTFET) is designed for improving read and write stability. It uses two cross-coupled FNSBS-CNTFET for storing data, along with one access transistor connected with bit line (BL) and word line (WL) with minimum supply voltage therefore leakage current is reduced. By this, the proposed method reduces the delay of writing and reading cycles and to get better static noise margin (SNM) and controls precharge voltage. The proposed 5 FNSBS-CNTFET-SRAM is done in the HSPICE platform. Then the performance of the proposed 5T FNSBS-CNTFET-SRAM design is measured in terms of lower Read Delay by 24.97%, 18.04%, lower Write Delay by 20.83%, 19.06% and compared with existing methods like 10T CNTFET-SRAM, 8T CNTFET SRAM respectively.