Security of SoC firmware load protocols

Abstract

The security architecture of modern systems-on-a-chip (SoC) is complex and critical to be done right and quickly. SoC security architects feel an acute need for new tool-supported specification and validation technologies. Aiming to stimulate research into creation of these technologies, in this paper we provide some industrial insights and initial solutions. Focusing on a concrete non-trivial example of security sensitive firmware load protocols, we show how to: (1) concisely specify the communication between IP blocks; (2) model the adversary; (3) debug and verify the protocol.