A highly fault tolerant PLA architecture for realization of Boolean functions using failure-prone nanometer-scale device technologies

Abstract

This paper addresses the functional robustness and fault-tolerance capability of very-deep submicron CMOS and single-electron transistor (SET) circuits. A four-layer architecture is proposed for the design of very high-density digital systems using inherently unreliable and error-prone devices. Empirical results based on SPICE simulations show that the proposed design method improves fault immunity at transistor level. Graceful degradation of circuit performance allows recovery of information, where classical circuits would fail. The implementation of the proposed circuit architecture is shown as a regular and compact PLA-style matrix, allowing easy adaptability of the redundancy factor.