A High-Speed KECCAK Architecture Resistant to Fault Attacks

Abstract

The hash KECCAK algorithm has been proposed by the cryptographic architect with the goal to improve the hash security and the design hardware performances. The KECCAK hash algorithm has been implemented in the cryptographic circuits to ensure the hash security. It is become the standard hash algorithm used to determinate the information integrity. To protect the KECCAK hardware implementation against the fault attacks, a few numbers of fault detection schemes have been proposed. The fault attacks consist to create an erroneous KECCAK message to extract the hash secure data. In this paper, a new fault detection scheme based on modifying the KECCAK architecture is presented where the KECCAK round is divided into two blocks. We explain the details implementation of each blocks. The security simulation results demonstrate that our scheme reaches 99.995% fault coverage. In addition, the proposed scheme has been evaluated from viewpoint FPGA hardware implementation. The efficiency, the throughput, the frequency and the area have been evaluated and it is shown that our proposed scheme leads high frequency overhead and minimum area overhead compared to the previous work.