PRESSNoC: Power-Aware and Reliable Encoding Schemes Supported Reconfigurable Network-on-Chip Architecture

Abstract

We propose a Power-aware and Reliable Encoding Schemes Supported reconfigurable Network-on-Chip (PRESSNoC) architecture whereby an encoding can be selected by a REasoning And Learning (REAL) framework at run-time to fit the reliability and power requirements of the application and its execution environment. PRESSNoC was implemented on a Xilinx Virtex 4 FPGA device, which required 25.5% lesser number of slices compared to the traditional NoC with a full-fledged encoding method. The average benefit to overhead ratio of the proposed architecture is greater than that of the traditional architecture by 71%, 32% ,a nd277% when we consider the individual effects of interference rate per instruction, application domains, and system characteristics, respectively. It shows we have higher probability toward the reduction of crosstalk interferences and dynamic power consumption at the same overheads by using the proposed architecture. I. INTRODUCTION Due to advanced process technologies, the decreasing dis- tance between wires has increased the gate count capacity of a chip, but it has also led to significant crosstalk interfer- ences among adjacent wires. Crosstalk is usually caused by undesired conductive coupling from one channel to another. This problem becomes more severe in a Network-on-Chip (NoC) because of the large number of wires used for parallel communication. Further, in advanced process technologies, the ratio of wire to gate power consumption has increased significantly such that the power consumed by wires can no longer be neglected in any power estimation model. Due to the large number of wires in an NoC, the high dynamic power consumption incurred due to parallel communications among concurrently running applications has also become a design issue. To reduce crosstalk interferences and dynamic power con- sumption in an NoC, a well-known and popular method is to reduce the switching activity by means of data encoding schemes which target at reducing the occurrence of spe- cific data patterns such as two/three adjacent transitions and two/three aggressors that may cause crosstalk interferences or high dynamic power consumption. Nevertheless, the tra- ditional encoding methods are fixed, that is, they cannot adapt to the varying requirements of different applications, domains, and systems. The proposed infrastructure mainly includes a novel reconfigurable NoC architecture design, called Power- aware and Reliable Encoding Schemes Supported reconfig- urable Network-on-Chip (PRESSNoC), four data encoding strategies, and an intelligent strategy selection method with reasoning and learning. PRESSNoC supports the dynamic reconfiguration (9) of encoding methods to fit the require- ments of the working set of applications connected to it. The encoding methods include DUal Cycle Encoding (DUCE), Transition and Aggressor reduced Encoding (TAE), Single Additional Flit Encoding (SAFE), and Dual Additional Flit Encoding (DAFE), which differ in the provision of reliability, power efficiency, hardware resource overhead, and perfor- mance overhead. The encoding strategy selection in PRESS- NoC is achieved through a REasoning And Learning (REAL) framework that can dynamically investigate the tradeoffs among reliability requirements, power reduction requirements, performance overhead, and hardware resource utilization. The rest of the paper is organized as follows. Section II summarizes the state-of-the-art reconfigurable NoC designs. In Section III, we describe the proposed encoding strategies with a REAL framework. Experiment results are shown in Section IV. Finally, we conclude in Section V with some future work.