V. Jacintha, K.H. Shakthimuruzan, V. Kripakaran, S. Lokeshwaran
{"title":"FPGA Based Dual Redundancy CAN Controller with Fault Tolerance","authors":"V. Jacintha, K.H. Shakthimuruzan, V. Kripakaran, S. Lokeshwaran","doi":"10.1109/ICEES.2018.8443204","DOIUrl":null,"url":null,"abstract":"Ahstract- CAN (Controller Area Network) has emerged to be one among the most prominent data bus which has the following features, which are anti-interference capability, reduced cost as well as ease of maintenance. Hence in this paper we propose, a Dual Redundancy CAN-bus Controller (DRCC) rooted strongly on FPGA chip. Earlier the method for dual redundancy CAN-bus is accomplished only with the help of software, which obviously has the following disadvantages such as reliability issues and meager real-time performance. Hence, a hardware based redundancy management unit is successfully brought forth in this paper, which is developed on the error handling rule with a CAN specification version of 2.0. A multicore redundant FPGA based CAN-bus Controller (DRCC) is developed. The design is incorporated into a Altera Cyclone II chip for testing purpose and it is confirmed that the design meets the requirement needed for high realistic achievement and dependability, with emerging trends for the forthcoming years.","PeriodicalId":134828,"journal":{"name":"2018 4th International Conference on Electrical Energy Systems (ICEES)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 4th International Conference on Electrical Energy Systems (ICEES)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICEES.2018.8443204","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
Ahstract- CAN (Controller Area Network) has emerged to be one among the most prominent data bus which has the following features, which are anti-interference capability, reduced cost as well as ease of maintenance. Hence in this paper we propose, a Dual Redundancy CAN-bus Controller (DRCC) rooted strongly on FPGA chip. Earlier the method for dual redundancy CAN-bus is accomplished only with the help of software, which obviously has the following disadvantages such as reliability issues and meager real-time performance. Hence, a hardware based redundancy management unit is successfully brought forth in this paper, which is developed on the error handling rule with a CAN specification version of 2.0. A multicore redundant FPGA based CAN-bus Controller (DRCC) is developed. The design is incorporated into a Altera Cyclone II chip for testing purpose and it is confirmed that the design meets the requirement needed for high realistic achievement and dependability, with emerging trends for the forthcoming years.