On-chip multiple superscalar processors with secondary cache memories

Abstract

The development of an experimental high-performance microprocessor chip based on a 0.3- mu m BiCMOS technology is discussed. It is designed to operate at a 250-MHz clock rate. It includes two processors, each of which executes two instructions in parallel. The chip performs 1000 MIPS when instructions and data are fetched from primary caches. It also includes a four-wave interleaved secondary cache assessed in parallel according to a split-bus protocol, to reduce shared memory conflicts. The VLSI architecture and design results of this chip are described.<>