Flip chip overview

Abstract

Despite the current high level of interest in flip chip technology there remain many obstacles to its widespread acceptance. These include among others: 1) the cost of the bumping, 2) the cost for redistribution 3) reliability data on the assembled product, 4) compatibility issues with dielectrics, and 5) known good die. This paper describes processes that place bumps either on the existing I/O pattern, or on a redistributed connection footprint. The problem of added cost due to redistribution will be dealt with through the use of a novel fabrication process that allows the formation of the redistributed trace and the bump in a single mask. A test method is also described which provides a full metallurgical contact for burn-in and test. Full metallurgical contact has been recognized as the technique that provides the highest quality tested die. Some of the concurrent activities at MCNC associated with the Flip Chip Technology Center (FCTC) are also described.