T. Ohshima, N. Yamamoto, T. Ichioka, T. Kimura, Y. Sano
{"title":"Application of phase-shifting mask technology to 0.17/spl mu/m-gate GaAs MESFET for ultra high speed IC's","authors":"T. Ohshima, N. Yamamoto, T. Ichioka, T. Kimura, Y. Sano","doi":"10.1109/DRC.1994.1009448","DOIUrl":null,"url":null,"abstract":"Then W-Al was anisotropically etched by the electron cyclotron resonance (ECR) plasma using the Al pattern as a mask, where the difference between the resist spacing and the gate length was less than 0.02pm. A standard deviation of 0.17pm W-AI gate pattern obtained was as small as 0.019pm (9.5%) over a 3-inch wafer. After the gate formation, ion implantations of Si and C were performed to form n+-region and buried p-region which were self-aligned to the gate. This structure successfilly suppressed the short channel effect without sacrificing its high speed performance, namely, without increasing the parasitic capacitance. Fabricated 0.17pm-gate GaAs MESFETs have shown the averaged maximum transconductance of 622mmS/mm with the standard deviation of lOmmS/mm (1.6%) at the drain voltage of 1V. The uniformity of the threshold voltage was also good, and the standard deviation was 28mV over a 3-inch wafer. The DCFL (Direct-Coupled FET Logic) inverter implemented by this device has shown a propagation delay of 10.4pdgate with a power dissipation of 2.34mW/gate at the supply voltage of 2V as averaged values over a 3-inch wafer. These standard deviations were 0.28ps/gate (2.7%) and 0.053mW/gate (2.3%), respectively. As the highest value, we have observed the propagation delay of 7.6pdgate at a supply voltage of 1OV. Using this device we have fabricated 8: 1 multiplexer and 1 :8 demultiplexer, and obtained a stable operation at lOGb/s at a power dissipation as low as 1.5W and 2.0W, respectively. The demultiplexer has operated even at 14Gb/s, which is one of the best results ever reported. A yield of these IC's was over 50%, which was due to the high uniformity in the characteristics of the MESFETs. Finally, we have confirmed that the fabrication process of 0.17pm-gate GaAs MESFET based on the phase-shifting mask technology is promising for the ultra high speed digital IC application. Next, Al was evaporated and lifted-off","PeriodicalId":244069,"journal":{"name":"52nd Annual Device Research Conference","volume":"103 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1994-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"52nd Annual Device Research Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DRC.1994.1009448","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
Then W-Al was anisotropically etched by the electron cyclotron resonance (ECR) plasma using the Al pattern as a mask, where the difference between the resist spacing and the gate length was less than 0.02pm. A standard deviation of 0.17pm W-AI gate pattern obtained was as small as 0.019pm (9.5%) over a 3-inch wafer. After the gate formation, ion implantations of Si and C were performed to form n+-region and buried p-region which were self-aligned to the gate. This structure successfilly suppressed the short channel effect without sacrificing its high speed performance, namely, without increasing the parasitic capacitance. Fabricated 0.17pm-gate GaAs MESFETs have shown the averaged maximum transconductance of 622mmS/mm with the standard deviation of lOmmS/mm (1.6%) at the drain voltage of 1V. The uniformity of the threshold voltage was also good, and the standard deviation was 28mV over a 3-inch wafer. The DCFL (Direct-Coupled FET Logic) inverter implemented by this device has shown a propagation delay of 10.4pdgate with a power dissipation of 2.34mW/gate at the supply voltage of 2V as averaged values over a 3-inch wafer. These standard deviations were 0.28ps/gate (2.7%) and 0.053mW/gate (2.3%), respectively. As the highest value, we have observed the propagation delay of 7.6pdgate at a supply voltage of 1OV. Using this device we have fabricated 8: 1 multiplexer and 1 :8 demultiplexer, and obtained a stable operation at lOGb/s at a power dissipation as low as 1.5W and 2.0W, respectively. The demultiplexer has operated even at 14Gb/s, which is one of the best results ever reported. A yield of these IC's was over 50%, which was due to the high uniformity in the characteristics of the MESFETs. Finally, we have confirmed that the fabrication process of 0.17pm-gate GaAs MESFET based on the phase-shifting mask technology is promising for the ultra high speed digital IC application. Next, Al was evaporated and lifted-off