Nedson J. Maia, A. D. R. Sánchez, R. Moreno, T. Pimenta, L. H. C. Ferreira
{"title":"A Low Power CMOS Operational Transconductance Amplifier with Improved CMRR","authors":"Nedson J. Maia, A. D. R. Sánchez, R. Moreno, T. Pimenta, L. H. C. Ferreira","doi":"10.1109/ICM50269.2020.9331501","DOIUrl":null,"url":null,"abstract":"This work proposes a new low power Operational Transconductance Amplifier (OTA) topology. The rejection to common-mode signals is achieved by adding parallel transistors to input MOS transistors in order to increase the Common Mode Rejection Ratio (CMRR). It achieves a gain of 87.34 dB at 9.65 μW power consumption. The article presents a comparison to other OTA topologies. The proposed OTA was designed for the IBM 0.13 μm CMOS technology.","PeriodicalId":243968,"journal":{"name":"2020 32nd International Conference on Microelectronics (ICM)","volume":"78 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 32nd International Conference on Microelectronics (ICM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICM50269.2020.9331501","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
This work proposes a new low power Operational Transconductance Amplifier (OTA) topology. The rejection to common-mode signals is achieved by adding parallel transistors to input MOS transistors in order to increase the Common Mode Rejection Ratio (CMRR). It achieves a gain of 87.34 dB at 9.65 μW power consumption. The article presents a comparison to other OTA topologies. The proposed OTA was designed for the IBM 0.13 μm CMOS technology.