A high-speed fair scalable scheduling architecture

Abstract

This paper proposes a high-speed fair scalable scheduling architecture (FSSA) based on input queued switches, which can be implemented on a 64 x 64 scheduler. Compare with the ordinary SSA, the FSSA evenly distributes the starts of new scheduling rounds to different cell times in guarantee of a more balanced scheduling pattern. The simulation results show that the FSSA has a better performance in latency than SSA especially under low traffic load and the synthesis and post simulation results indicate that the data rate of each channel can be up to 800 Mbps. Therefore, the implementation of FSSA is applicable to high-speed scalable switches.