Multiple control fault testing in digital systems with high-level decision diagrams

Abstract

A new method of high-level test generation for control faults in digital systems is proposed. High-level faults of any multiplicity are assumed to be present, however, there is no need to enumerate them. A novel concept of test groups which has the goal to prove the correctness of a part of the system's functionality instead of keeping track of fault coverage during test generation as in the traditional case is elaborated. The method can be regarded as a generalization of the logic level test pair approach for identifying fault-free wires in gate-level networks to a high-level identification of fault-free functional blocks. To cope with the complexity of multiple fault masking mechanisms, high-level decision diagrams are used. A method for optimizing test length was developed with no negative impact on the immunity regarding possible fault masking, and the estimates of the gain in test length were given.