Leakage Power Analysis attacks: Well-defined procedure and first experimental results

Abstract

In this paper, attacks aiming at recovering the secret key of a cryptographic core from measurements of its static (leakage) power are presented. These attacks exploit the dependence of the leakage current of CMOS Integrated Circuits (ICs) on their inputs (e.g., the secret key of a cryptographic circuit). For this reason, these novel attacks are referred to as Leakage Power Analysis (LPA) attacks in this paper. Since the leakage power increases much faster than the dynamic power at each new technology node, LPA attacks are shown to be a serious threat to information security of cryptographic circuits in sub-100 nm technologies. For the first time in the literature, a well-defined procedure to perform LPA attacks is presented. Advantages and measurement issues are also analyzed in comparison with traditional Power Analysis attacks based on dynamic power measurements. An experimental attack to a register is finally performed for the first time.