High quality atpg for delay defects

Abstract

The paper presents a novel technique for generating effective vectors for delay defects. The test set achieves high path delay fault coverage to capture small- distributed delay defects and high transition fault coverage to capture gross delay defects. Furthermore, non-robust paths for ATPG are filtered (selected) carefully so that there is a minimum overlap with the already tested robust paths. A relationship between path delay fault model and transition fault model has been observed which helps us reduce the number of non-robust paths considered for test generation. To generate tests for robust and non-robust paths, a deterministic ATPG engine is developed. Clustering of paths has been done in order to improve the test set quality. Implications were used to identify the untestable paths. Finally an incremental propagation based ATPG is used for transition faults. Results for ISCAS'85 and full-scan ISCAS'89 benchmark circuits show that the filtered non- robust path set can be reduced to 40% smaller than the conventional path set without losing delay defect coverage. Clustering reduces vector size in average by about 40%.