Planar inductors with subdivided conductors for reducing eddy current effects

Abstract

In this work, a method for reducing eddy current effects in planar inductors is presented. This patent pending method has already been demonstrated to be effective for microstrip lines. In this work we present measurements that demonstrate that the maximum quality factor of a planar inductor in a standard 0.35 /spl mu/m CMOS process with three metal layers could be improved by up to 35% to a value of 8.0.