Enhanced Micro-Scheduling and Hardware Acceleration Architecture for High Data Rate WPAN MAC

Abstract

In this paper, we propose a hardware scheduling method and an acceleration architecture for a high data rate WPAN MAC. The proposed micro-scheduling method is performed using real time beacon parsing and time slot assignment techniques for the MAC superframe. It also includes hardware acceleration features such as media speed security engine and multiple block acknowledgment function. By adopting several hardware features, we can minimize the software intervention and maximize the overall system performance.