{"title":"Real-time data reorganizer for the D0 central fiber tracker trigger system at Fermilab","authors":"S. Rapisarda, N. Wilcer, J. Olsen","doi":"10.1109/NSSMIC.2002.1239299","DOIUrl":null,"url":null,"abstract":"A custom digital data mixer system has been designed to reorganize, in real time, the data produced by the Fermilab D0 Scintillating Fiber Detector. The data is used for the Level 1 and Level 2 trigger generation. The mixer system receives the data from the front-end digitization electronics over 320 Low Voltage Differential Signaling (LVDS) links running at 371 MHz. The input data is de-serialized down to 53 MHz by the LVDS receivers, clock/frame re-synchronized and multiplexed in Field Programmable Gate Arrays (FPGAs). The data is then reserialized at 371 MHz by LVDS transmitters over 320 LVDS output links and sent to the electronics responsible for Level 1 and Level 2 trigger decisions. The Mixer System processes 311 Gigabits per second of data with an input to output delay of 200 nanoseconds.","PeriodicalId":385259,"journal":{"name":"2002 IEEE Nuclear Science Symposium Conference Record","volume":"8 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2002 IEEE Nuclear Science Symposium Conference Record","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NSSMIC.2002.1239299","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
Abstract
A custom digital data mixer system has been designed to reorganize, in real time, the data produced by the Fermilab D0 Scintillating Fiber Detector. The data is used for the Level 1 and Level 2 trigger generation. The mixer system receives the data from the front-end digitization electronics over 320 Low Voltage Differential Signaling (LVDS) links running at 371 MHz. The input data is de-serialized down to 53 MHz by the LVDS receivers, clock/frame re-synchronized and multiplexed in Field Programmable Gate Arrays (FPGAs). The data is then reserialized at 371 MHz by LVDS transmitters over 320 LVDS output links and sent to the electronics responsible for Level 1 and Level 2 trigger decisions. The Mixer System processes 311 Gigabits per second of data with an input to output delay of 200 nanoseconds.