Energy-Efficient Design of Approximated Full Adders

Abstract

This work analyses a set of approximate full adder circuits in 7nm FinFET device technology in order to identify how energy-efficient these designs are for different voltage operation points. The behavior in a specific environment with voltage scaling is compared to conventional exact adders. The results allow designers access to the pros and cons of each design in error-tolerant applications. Considering the impact on delay and power consumption, approximate XNOR and PTL based FAs showed increase in PDP for all voltages applied. However, Mirror Adder inspired approximate designs showed a reduction in PDP at 0.4V. The PDP for buffer approximated FAs remained constant throughout voltage scaling.