FPGA implementation of a three-way asynchronous DDR2 memory controller

G. Daou, A. Kassem, M. Hamad, C. El-Moucary
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引用次数: 2

Abstract

This paper describes the implementation of a three-way asynchronous Double Data Rate (DDR2) memory controller using a Field-Programmable Gate Array (FPGA). The objective is to replace the memory buffer in a PC-based oscilloscope, where a First-In First-Out (FIFO) stack was used. The digital oscilloscope is used for measuring and reconstructing eye diagrams for high speed signals, such as Ethernet (1.25, 10.3125 Gbps), PCI-Express (2.5, 5.0, 6.125 Gbps), SATA (1.5, 3.0 Gbps), etc... Replacing the stack with DDR2, improves the quality of the eye diagram, which describes parameters of the input signal, for the DDR2 higher data transfer speed and larger memory size.
FPGA实现的一种三向异步DDR2存储器控制器
本文介绍了一种采用现场可编程门阵列(FPGA)实现的三向异步双数据速率(DDR2)存储器控制器。目标是替换基于pc的示波器中的内存缓冲区,其中使用先进先出(FIFO)堆栈。数字示波器用于测量和重建高速信号的眼图,如以太网(1.25,10.3125 Gbps), PCI-Express (2.5, 5.0, 6.125 Gbps), SATA (1.5, 3.0 Gbps)等。用DDR2代替堆栈,提高了描述输入信号参数的眼图的质量,因为DDR2具有更高的数据传输速度和更大的内存容量。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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