Parity Preserving Reversible Design Using FinFETs

Abstract

In this article we have developed parity preserving logic with the help of FinFET using reversible logic. Parity preserving reversibility allows the design to be fault tolerant as well as power efficient. Performance of the proposed design is validated by implementing full adder and ALU using FinFET with Cadence Virtuoso at 10nm. The design is approximately 50% better than the previously proposed designs along with preserving parity and reversibility.