Plane bounce in high-speed single-ended signaling I/O interfaces

Abstract

Single-ended signaling is a popular choice for memory interface designs, due to its low pin-count requirement and slow DRAM process technology. Single-ended signaling requires a good current return path, in order to maintain high signal quality. Commonly used single-ended signaling schemes require both power and ground current return paths. In high-density memory interface systems, not all of the signals can be routed using a stripline with both power and ground planes. Using other non-stripline routing configurations can lead to voltage noise at some of the reference planes; referred to as plane bounce. This paper demonstrates that, while plane bounce may be significant in amplitude, its impact on the data signal is not as critical as previously thought. Various channel topologies are used to support this assertion.