Collection of high-level microprocessor bugs from formal verification of pipelined and superscalar designs

International Test Conference, 2003. Proceedings. ITC 2003. Pub Date : 2003-09-30 DOI:10.1109/TEST.2003.1270834

M. Velev

引用次数: 29

Abstract

The paper presents a collection of 93 different bugs, detected in formal verification of 65 student designs that include: 1 ) singleissue pipelined DLX processors; 2 ) extensions with exceptions and branch prediction; and 3) dual-issue superscalar implementations. The processors were described in a high-level HDL, and were formally verified with an automatic tool flow. The bugs are analyzed and classified, and can be used in research on microprocessor testing.

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从流水线和超标量设计的正式验证中收集高级微处理器错误

本文介绍了在65个学生设计的正式验证中发现的93个不同的错误，包括:1)单问题流水线DLX处理器;2)带异常和分支预测的扩展;3)双问题超标量实现。用高级HDL描述了处理器，并使用自动工具流进行了正式验证。对这些缺陷进行了分析和分类，可用于微处理器测试的研究。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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International Test Conference, 2003. Proceedings. ITC 2003.

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