PHYSICS OF MOSFET NANOTRANSISTORS: FUNDAMENTAL LIMITS AND RESTRICTIONS

Abstract

In the last one from the series of the tutorial review articles, devoted to physics of modern nanotransistors and aimed to serve reseachers, ingeneers, students and teachers in the universities, it is demonstrated that the existence of the minimal energy for recording of 1 bite of information leads to fundamental restriction on minimal MOSFET channel length and on minimal time of transistor swithching. The obtained simple estimation Lmin = 1.2 nm (for room temperature) is somewhat lower, than in reality, and it looks like that Si FETs with a channel shorter than 2.5–3 nm would newer be fabricated. This correlates with the results of numerical modeling of electron transport through the channel, which demonstrate that for short channels the greater part of current passes by tunneling below the barrier top, and the transistor loses its functionality, because the current in source-drain circuit is no longer governed by gate voltage.