Fabrication of epitaxial tunnel junction on tunnel field effect transistors

Abstract

With an increase in the amount of collected and modified data in today’s "big data" era, the demand for calculation resources in both "cloud" and "edge" has also increased. Circuits consume high power when calculating large amount of data. Presently, advanced microchips consume over 100 W of power, which is a critical problem of realizing the big data/IoT/AI concepts. Reducing the operation voltage (V DD ) of devices is the most effective way to reduce power consumption of chips. The IRDS roadmap predicts ways to simultaneously reduce V DD and "subthreshold swing" (SS) [1] . However, the SS of a MOSFET is limited to 60 mV/decade at room temperature because of its operation mechanism [2] . Thus, remarkably reducing the MOSFET operating voltage is difficult. To overcome this problem, novel devices having different operation mechanisms from the MOSFET are required [3] – [5] .