Bridging RTL and gate: correlating different levels of abstraction for design debugging

Abstract

In order to help designers debug and verify a Gate-Level design that is generated from a Register-Transfer-Level (RTL) reference model, it is important to bridge the knowledge gap between the two levels of abstraction. In this paper, we present a comprehensive approach to establish correspondence of design objects between a Gate-Level implementation and its golden reference model specified at RTL. We consider both common logic synthesis transformations and advanced logic optimizations that are applied in the generation of the Gate-Level implementation, while not being restricted to any specific synthesis tool. Our approach integrates a set of techniques to compare the similarities in names, structures, and functions between the Gate-Level implementation and the RTL counterpart We use large industrial designs to demonstrate the effectiveness of our approach and show how our design correlation tool can help designers solve their problems such as Engineering Change Order, Timing Closure, and Emulation Visualization.