S. Afroz, T. Vasen, Brian Novak, Ken A. Nagamatsu, P. Shea, S. Wanis, R. Howell, Josephine B. Chang
{"title":"Frequency Performance Improvements for SLCFET Amplifier Through Device Scaling","authors":"S. Afroz, T. Vasen, Brian Novak, Ken A. Nagamatsu, P. Shea, S. Wanis, R. Howell, Josephine B. Chang","doi":"10.1109/BCICTS50416.2021.9682467","DOIUrl":null,"url":null,"abstract":"This paper reports frequency performance improvements in Superlattice Castellated Field Effect Transistor (SLCFET) amplifier through device scaling. Device scaling incorporates the variations in castellation ridge width, castellation trench width, castellation length, gate stem length, gate hat length, gate offset, gate dielectric thickness, and passivation thickness. Highest ${f_{T}}$ and Fmax (70GHz/150GHz) values were achieved on devices with shortest castellation length. Shortening castellated access region reduces series resistance resulting in improved frequency performance. Thinner gate dielectric improves transconductance resulting enhancement in frequency performance as well.","PeriodicalId":284660,"journal":{"name":"2021 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/BCICTS50416.2021.9682467","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
This paper reports frequency performance improvements in Superlattice Castellated Field Effect Transistor (SLCFET) amplifier through device scaling. Device scaling incorporates the variations in castellation ridge width, castellation trench width, castellation length, gate stem length, gate hat length, gate offset, gate dielectric thickness, and passivation thickness. Highest ${f_{T}}$ and Fmax (70GHz/150GHz) values were achieved on devices with shortest castellation length. Shortening castellated access region reduces series resistance resulting in improved frequency performance. Thinner gate dielectric improves transconductance resulting enhancement in frequency performance as well.