Integrated Wafer and Die Level Simulation of Back End of Line Chemical Mechanical Polishing Processes

Abstract

The Chemical Mechanical Polishing (CMP) variation on a die is a function of the die's location on the wafer [1]. Consequently, the number of CMP hotspots and the hotspot locations can vary from die-to-die on a given wafer. In this paper, we demonstrate the accuracy of Cadence's integrated wafer and die level CMP model in predicting the CMP variation on multiple dies across product chip wafers.