Solder void reduction on solder die attach for SIP-LGA

Abstract

SIP or System In Package as its name suggests is a package that consist of a combination of dies (asics, memory, mosfets etc), passive components or shielding in an IC package format. Due to design and layout complexity, it is normally required to be housed in a substrate based packaging. The connection of silicon die to package can be in the form of wire-bond, flipchip, epoxy die attach,or solder die attach. In cases where solder die attach is used, the challenge would lie in the ability to produce the least die attach void. The presence of solder void underneath the die is not desirable as it has thermal and in some cases electrical impact in the performance of the device. Solder voids, depending on its magnitude can also reduce the reliability and functionality of the device. There are many methods of applying solder namely using solder preform . dispensing solder paste or screen printing solder paste. Screen printing is the most desirable process due to its uph and ability in controlling the solder volume. This paper discusses in detail some of the factors that affect the solder voids percentage and look into ways to improve the amount of solder void underneath a die by 50%.