Y. Hattori, K. Nakashima, M. Kuwahara, T. Yoshida, S. Yamauchi, H. Yamaguchi
{"title":"Design of a 200V super junction MOSFET with n-buffer regions and its fabrication by trench filling","authors":"Y. Hattori, K. Nakashima, M. Kuwahara, T. Yoshida, S. Yamauchi, H. Yamaguchi","doi":"10.1109/WCT.2004.239903","DOIUrl":null,"url":null,"abstract":"A new super junction trench MOSFET, which has n-buffer regions between trench gates and n columns, was designed and demonstrated. In this structure, the specific on-resistance (R/sub ON/) does not increase as long as the trench gate bottom is covered with the n buffer, even though the gate position shifts from the designed one. The drift region, consisting of p/n columns in the structure, were formed by a trench filling epitaxial method. The fabricated SJ-MOSFET with a fine cell pitch of 4 /spl mu/m showed an RON of 2.3 n/spl Omega/.cm/sup 2/ at a breakdown voltage (V/sub BR/) of 203 V. The R/sub on/ is 35% lower than that of the silicon limit.","PeriodicalId":303825,"journal":{"name":"2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs","volume":"20 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"22","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/WCT.2004.239903","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 22
Abstract
A new super junction trench MOSFET, which has n-buffer regions between trench gates and n columns, was designed and demonstrated. In this structure, the specific on-resistance (R/sub ON/) does not increase as long as the trench gate bottom is covered with the n buffer, even though the gate position shifts from the designed one. The drift region, consisting of p/n columns in the structure, were formed by a trench filling epitaxial method. The fabricated SJ-MOSFET with a fine cell pitch of 4 /spl mu/m showed an RON of 2.3 n/spl Omega/.cm/sup 2/ at a breakdown voltage (V/sub BR/) of 203 V. The R/sub on/ is 35% lower than that of the silicon limit.