Power supply noise investigation of a multilayered IC package: full wave simulation and model validation

Abstract

The present paper investigates the power supply noise in multilayered IC packages and analyzes the effect of shorting vias. A full wave code, based on the Finite Integration Technique (FIT), is used for the numerical simulations and it is validated by means of measurements. Furthermore two different solvers are employed to verify the accuracy of the proposed model: time domain and frequency domain. Some results are addressed: 1) the use of shorting vias allows achieving more than 50% noise suppression and 2) the mitigation level is related to the distance of the shorting vias from the signal via. The signal integrity on a signal propagating from the top layer to the bottom layer of the considered IC package is studied by means of Scattering parameters (S-parameters) and time domain reflectometry (TDR). In particular it is found that the TDR evaluated for the model with closer shorting vias results in a larger impedance variation.