An improved 40 Gb/s CDR with jitter-suppression filters and phase-compensating interpolators

Abstract

An improved clock data recovery (CDR) operating at 40 Gb/s is implemented in 65 nm CMOS technology. Passive low-pass filters (LPFs) with adaptively adjusted bandwidth are introduced into the data-sampling path to automatically balance jitter tracking and jitter suppression for data decisions. Additionally, a time-averaging based compensating phase interpolator (PI) is proposed to not only improve the phase-step uniformity but also reduce phase-spacing drifting between edge and data sampling clocks. Measurement results show that different bandwidths for jitter transfer (4 MHz) and jitter tolerance (20 MHz) can be obtained. The total jitter of recovered clocks for edge-sampling and data-sampling are 11.48 ps and 7.66 ps, respectively. Meanwhile, the introduced jitter-suppression filters improve the maximum tolerable amplitude of sinusoidal jitter from 0.31 UI to 0.41 UI at 100 MHz.