On-chip RLC interconnections effects on high speed transceivers

Abstract

The rapid growth of microelectronics constantly presents new challenges to the IC designer. The physical and dynamic characteristics of wires on a die begin to dictate the topology of an integrated circuit. Second- and third-order effects are becoming important in designs built on processes smaller than 400 nm. In this paper we try to present the influence of the parasitic layout elements by showing the difference between RC and RLC parasitic extraction and simulation and their effects on the performance of a limiting amplifier used in the optic fiber transceivers. The evaluation was done using a standard 150 nm technology.