An Efficient Digital Nonlinear Self-Interference Cancellation Architecture for Full-Duplex System

Abstract

Due to the high self-interference from the transmitter, the deployment of the full-duplex system is still far from trivial. The digital self-interference cancellation (DSIC) is the main means of dealing with self-interference. The performance of the typical DSIC is constrained by the elimination capacity of the nonlinear distortion. Based on the characteristic of the nonlinear signal caused by power amplifiers, memory polynomial can portray it properly. Encouraged by this characteristic, we propose a novel DSIC structure to achieve a better efficiency. The auxiliary receiver chain named as the pre-processing stage in this paper is included to process the linear part of the self-interference signal. Moreover, the pro-processing stage provides the convergence direction of the adaptive filter. Shorter convergence time and lower mean square error (MSE) are reached. The numerical results furnished by the realistic and rigorous simulations substantiate the efficiency of the proposed architecture.