Poly-residue-induced contact failures in 0.18 /spl mu/m technology

Abstract

During the qualification of a 0.18 /spl mu/m SRAM process technology, severe yield loss due to random single bit and dual bit failures were encountered. This occurred not only at wafer sort, as failures of these types had also manifested themselves as time-dependent since some of these failures emerged only after certain kinds of reliability tests. Though bit mapping using the MOSAID tester always identified the bit location, the failure analysis was still difficult due to the increasing susceptibility of 0.18-micron devices to the fluctuation of device parameters and process related defects. Moreover, the increasing complexity and multiple metal layers with stacked via structures have also made FA even tougher. Usually a combination of several FA techniques must be used to identify the defect. With no exception in this case, an open contact in the SRAM cell that had led to single and dual-bit failures was isolated by the effective passive voltage contrast (PVC) technique.