Architectural exploration and optimization for counter based hardware address generation

Abstract

A set of automated system level techniques is presented for architectural exploration and optimization of counter based address generation units in real time signal processing systems. The goal is to explore different architectural alternatives available when mapping array references in order to select the most promising ones in area cost. The techniques are demonstrated on realistic test-vehicles, showing that architectural decision at early stages of the design process, can have a very large impact on the resulting area figure.