Process-induced-strain maximization of nano-scale silicon-on-sapphire high-k gate-dielectric MOSFETs by adjusting device aspect ratio

Abstract

In the current paper, a systematic study is presented of step-by-step process-induced stress variation of a Sapphire/Silicon/high-k MOSFET, for various aspect ratios, W/L. A substantial value of compressive stress of about 1 GPa, suitable for hole mobility enhancement, has been obtained. It is observed that the nature of the induced stress depends heavily on device dimensions. The study has been carried out for gate lengths ranging from 100 nm to 10 nm. For a particular gate length, a definite range of W/L ratios has been detected for which the process-induced stress remains uniaxial and therefore acceptable. It is also shown that, for smaller gate lengths the acceptable range of W/L ratios expands, whereas it shrinks towards the higher ratios only, for longer gate lengths.