InP-based HEMTs for high speed, low power circuit applications

Abstract

Processes for the monolithic integration of enhancement- and depletion-mode HEMTs (E/D-HEMTs) in the lattice matched InP material system are described. Using the buried Pt gate technology, 0.3 /spl mu/m gate-length E-HEMTs exhibiting a threshold voltage of +167 mV and a maximum extrinsic transconductance, g/sub mext/, of 700 mS/mm are demonstrated. D-HEMTs with corresponding device parameters of -443 mV and 462 mS/mm are presented. Unity current gain cut-off frequencies of-over 95 GHz were obtained for these devices. Implementation of a divide-by-four prescaler in the direct coupled FET logic technology based on E- and D-HEMTs is demonstrated.