A new approach of multi voltage and adaptive voltage scaling techniques for 16 nm FinFET RISC processor

D. Babayan, E. Babayan, Sevak Antonyan, Ani Salmasyan, E. Kagramanyan, A. Avetisyan
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引用次数: 2

Abstract

Currently in deep sub-micron technologies such as 16 nm and smaller, requirement of portable devices focus designers' attention on low power design of CMOS circuits and systems, using different low power techniques, trying to decrease dynamic and/or leakage power. One of the widely employed power optimization methods is multi voltage design, used to reduce power by dividing IC into voltage IC domains. This paper presents a new approach of multi voltage design technique, generalizing it, to use “n” voltage domains with “n” different supply voltages, providing efficient power reduction of digital systems such as processor. Basically, voltage areas match sub modules of processor with addition of modified version of adaptive voltage scaling.
一种用于16nm FinFET RISC处理器的多电压和自适应电压缩放技术新方法
目前,在16纳米及更小的深亚微米技术中,便携式设备的需求将设计人员的注意力集中在CMOS电路和系统的低功耗设计上,采用不同的低功耗技术,试图降低动态和/或泄漏功率。多电压设计是一种广泛应用的功耗优化方法,通过将集成电路划分为多个电压域来降低功耗。本文提出了一种新的多电压设计方法,将其推广到使用n个不同电源电压的n个电压域,为处理器等数字系统提供有效的功耗降低。基本上,电压区域匹配处理器的子模块,并增加了自适应电压缩放的改进版本。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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