Efficient parallel memory organization for turbo decoders

Abstract

An efficient turbo decoder must access memory in parallel and with two different access patterns. It is shown that the problem of accessing memory both with sequential and interleaved access patterns is analogous to the graph coloring problem. The derivation proves that the obtained graph is bipartite and, therefore, only two memory banks are required in theory. For practical implementations, a system with four memory modules and a buffer is proposed. It is shown that modest buffer length is sufficient for 3GPP standard interleavers. There is no performance degradation in the proposed system and the address generation and memory interfaces are of modest complexity.