A novel design of an asymmetric D-latch

Digest of Papers. 2004 Topical Meeting onSilicon Monolithic Integrated Circuits in RF Systems, 2004. Pub Date : 2004-09-08 DOI:10.1109/SMIC.2004.1398218

S. Trotta, J. Sundermeyer, N. Weber, J. Saurer

引用次数: 3

Abstract

The paper discusses design aspects of high speed asymmetric D-latches. It is shown how an asymmetric input clock signal can be used favorably to improve latch performance. Moreover. a completely asymmetric D-flipflop, which shows a static behavior at low frequency and a superdynamic behavior at very high speed, is presented.

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一种不对称d型锁存器的新设计

本文讨论了高速非对称d型闭锁的设计问题。它显示了一个不对称的输入时钟信号可以很好地用来提高锁存器的性能。此外。提出了一种完全不对称的d触发器，该触发器在低频时具有静态特性，在高速时具有超动态特性。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Digest of Papers. 2004 Topical Meeting onSilicon Monolithic Integrated Circuits in RF Systems, 2004.

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