Advanced source/drain technologies for parasitic resistance reduction

Abstract

To achieve high MOSFET drive current and speed in future technology nodes, potential bottlenecks such as high contact resistance should be resolved. In this paper, we review the technology solutions available for reducing the contact resistance between a metal silicide contact and the source/drain region. Novel approaches for reducing the electron and hole barrier heights between the metal silicide contact and the source/drain region in n- and p-FETs will be examined. Integration of these approaches in advanced device architectures will be shown.